Bit For The Ic Industry
IC s entering the market today is more complex in design with a higher integration density. This leads to increased vulnerability of the chip to problems such as cross talk noise contamination, and internal power dissipation. These problems reduce the reliability of the chip. Further more, with increased chip density, it becomes mo0re difficult to access test points on a chip for external testing. Also, testing procedures currently in use are time consuming, presenting a bottleneck for higher productivity [2]. These factors have led to the emergence of BIT in the semiconductor industry as a cost effective, reliable, and efficient quality control technique. Generally, adding testing circuitry on to the same IC chip increases the chip area requirement conflicting with the need for system miniaturization and power conception reduction. On the other hand, techniques have been developed to allow the circuit-under-test (CUT) to be tested using existing on-chip hardware, thus keeping the area overhead to a minimum.
About
The principal of Built-in-test and self-test has been widely applied to the design and testing of complex, mixed-signal electronic systems, such as integrated circuits (IC s) and multifractional instrumentation [1]. A system with BIT is characterized by its ability to identify its operation condition by itself, through the testing and diagnosis capabilities built into its in structure. To ensure reliable performance, testability needs to be incorporated into the early stage of system and product design. Various techniques have been developed over the past decades to implement the BIT technique. In the semiconductor, the objective of applying BIT is to improve the yield of chip fabrication, enable robust and efficient chip testing and better scope with the increasing circuit complexity and integration density. This has been achieved by having an IC chip generate its own test stimuli and measure the corresponding responses from the various elements within the chip to determine its condition.
Abstract
The increasing complexity of microelectronic circuitry, as witnessed by multi-chip modules and system-on-a-chip and the rapid growth of manufacturing process automation require, that more effective and efficient testing and fault diagnosis techniques be developed to improve system reliability, reduce system downtime, and enhance productivity.
Test Pattern Generator
Test pattern generators (TPG) are used for producing test vectors for the Cut inputs [2]. They are classified according to the type of test sequences generated, which fall under three categories:
· Exhaustive TPG
· Pseudorandom TPG
· Deterministic TPG
Pseudorandom TPG
Pseudorandom TPGs are more commonly used than Exhaustive TPGs. They have a lower hardware overhead, as only the LFSR is needed to generate the test vectors.
Deterministic TPG
Deterministic TPGs are used when the fault coverage provided by the pseudorandom test is not adequate and the circuit contains many ‘hard-to-detect’ faults. These are faults for which the test vectors corresponding to the fault take a very long time to appear in the test sequence.
Machine Tool Monitoring
The state of the machining process is reflected in the acoustic signatures produced by its components. Experienced machine operators can estimate the condition of a machine to with reasonable accuracy just by listening to the sound the tool makes. A similar fashion, microphones and acoustic emission (AE) sensors have been employed to quantitatively measure the acoustic features of the machine tool. Research works have been carried out on monitoring milling cutters using AE sensors that are structurally incorporated into the machine tool to facilitate continuous monitoring. One of the main problems associated with milling cutter monitoring is to identify an optimum location for the sensor.
Mixed Mode Bit
BIT methods are extensively used for testing embedded memories such as RAM and ALU because of the various failure modes that may involve with these chips eg. Memory cells stuck with 0 or 1, short circuitry, best coupling, redundant rows and columns are usually provided to replace failing locations [4]. Accordingly in addition to the past/fail testing, the BIT scheme used for memory testing may also have diagnostic capabilities in which a repair mechanism automatically reconfigures the memory cells based on the output from the BIT.
Conclusion
The philosophy of BIT has grown from a chip testing strategy in the semi conductor industry to an indispensable enabling tool for a wide range of manufacturing and consumer industries to better meet the ever-increasing demand for quality, safety and reliability. This trend will continue to grow supported by the continued development of enabling tools such as wireless data communication and component and system miniaturization using MEMS (micro electromechanical systems).
No comments:
Post a Comment